Lead physical design initiatives for multiple ASICs, optimizing layouts for area and performance. The ideal candidate will have expertise in Cadence and Synopsys EDA tools, with strong scripting capabilities in TCL, Perl, and Python for automated design flows. This role requires close collaboration with RTL designers and architects to implement design specifications, as well as partnership with fabrication vendors to ensure optimal layout, floorplanning, and overall design implementation. Experience in managing fab relationships and design optimization is essential.

Must have experience completing physical design on several chip projects15+ years experienceSystem VerilogSynopsis and Candence Tools

 

The successful candidate will lead physical design initiatives for multiple ASIC projects, focusing on:

• Developing and optimizing physical design flows to achieve optimal area utilization and performance metrics

• Implementing and iterating designs using industry-standard EDA tools from Cadence and Synopsys

• Creating and maintaining automation scripts using TCL, Perl, and Python to enhance design flow efficiency and integration

• Working closely with RTL designers and architects to translate design specifications into optimized physical implementations

• Managing relationships with fabrication partners, including:

Communicating design requirementsOptimizing layout and floor planningResolving technical challengesEnsuring quality control and adherence to specifications

The ideal candidate will possess strong expertise in physical design methodologies and demonstrate excellent communication skills to facilitate cross-functional collaboration between design teams and fabrication partners.