We are seeking a talented and detail-oriented Physical Backend Design Engineer to join our IC (Integrated circuit) development team. The role involves key aspects of physical design, including automated place and route, floorplanning, clock tree synthesis (CTS), static timing analysis (STA), power analysis, and physical verification (DRC/LVS). The ideal candidate will have a strong knowledge of physical design methodologies, experience with industry-standard tools, and a passion for delivering high-quality semiconductor solutions. 

You have: 

Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred)3+ years of experience in physical backend design for ICs. Complex chip designs through all stages of physical implementationExperience with tape-out of designs for advanced nodes is highly desirableStrong knowledge of physical design concepts, including place and route (PnR), clock tree synthesis (CTS), static timing analysis (STA) and power grid designExperience with physical verification tools like Cadence Pegasus or Mentor CalibreFamiliarity with parasitic extraction tools (e.g., StarRC, Quantus, Calibre xRC)Scripting skills in Python, Tcl, Perl, or Shell for automationRequired Tools: Cadence Innovus, Cadence Quantus, Cadence Tempus, Cadence Pegasus suite 

It would be nice if you also had: 

Experience with advanced process nodes (e.g., 7nm and below)Knowledge of low-power design techniques, such as multi-Vt, multi-Vdd, or clock gatingFamiliarity with DFT concepts and tools, Chip packaging and thermal analysis considerations, FinFET technology and 3D IC design methodologiesPerform floorplanning, partitioning, and optimization to achieve area, power, and performance targets.Execute automated place and route (PnR) using industry-standard tools to generate physical layouts.Implement clock tree synthesis (CTS), ensuring low skew and efficient clock distribution.Conduct static timing analysis (STA) to verify timing closure and ensure the design meets performance requirements.Perform power analysis, including IR drop and electromigration (EM) checks, to optimize power distribution networks.Conduct physical verification tasks, including design rule checks (DRC) and layout vs. schematic (LVS) checks, to ensure manufacturability and compliance with foundry standards.Collaborate with design, verification, and DFT teams to resolve physical design challenges and improve chip performance.Work closely with foundry teams to address process technology issues and implement best practices.